IBM unveils 0.7nm chip design with nearly 100 billion transistors

IBM unveiled a 0.7nm silicon chip design in June 2026 with a 3D stacked architecture that fits nearly 100 billion transistors into a form factor the company said is about the size of a human fingernail.

IBM said its 0.7nm design addresses physical manufacturing constraints by changing chip construction rather than only shrinking transistors. Jay Gambetta, director of IBM Research and an IBM Fellow, said the company is “reinventing how chips are built.”

IBM said the 0.7nm chip provides almost twice the density of the company’s 2nm chip unveiled in 2021. The company’s technical assessments indicated the design could improve performance by 50% and energy efficiency by 70% compared with that 2nm chip.

IBM said research presented earlier in June 2026 at the Very-Large-Scale Integration Symposium showed its nanostack architecture could reduce SRAM size and power consumption by 40%. IBM said the architecture arranges stacks vertically and staggers transistors to increase transistor count, and added that it validated the design through CMOS integration tests and demonstrations.